View CXL5508M_24240.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXL5508M/P
CMOS-CCD 1H Delay Line for PAL
Description The CXL5508M/P are CMOS-CCD delay line ICs that provide 1H delay time for PAL signals, including the external low-pass filter. Features * Single 5V power supply * Low power consumption 60mW (Typ.) * Built-in peripheral circuits Functions * 565-bit CCD register * Clock driver * Auto-bias circuit * Input clamp circuit * Sample-and-hold circuit Structure CMOS-CCD CXL5508M 8 pin SOP (Plastic) CXL5508P 8 pin DIP (Plastic)
Absolute Maximum Ratings (Ta = 25C) 6 V * Supply voltage VDD * Operating temperature Topr -10 to +60 C * Storage temperature Tstg -55 to +150 C * Allowable power dissipation PD CXL5508M 350 mW CXL5508P 480 mW Recommended Operating Condition (Ta = 25C) Supply voltage VDD 5 5% V Recommended Clock Conditions (Ta = 25C) * Input clock amplitude VCLK 0.3 to 1.0 Vp-p (0.5Vp-p typ.) * Clock frequency fCLK 8.867238 MHz * Input clock waveform Sine wave Input Signal Amplitude VSIG 500mVp-p (Typ.), 527mVp-p (Max.) (at internal clamp condition)
VGA
6
Blook Diagram and Pin Configuration (Top View)
AB VDD
8
7
Auto-bias circuit
Bias circuit
Timing circuit
CCD (565bit)
Clock driver Bias circuit (A) Output circuit (S/H 1bit) Bias circuit (B)
Clamp circuit
1
2
3
4
VGB
OUT
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
VSS
IN
CLK
5
E91101A7X-PS
CXL5508M/P
Pin Description Pin No. 1 2 3 4 5 6 7 8 Symbol IN VGB OUT VSS CLK VGA VDD AB I/O I I O -- I O -- O Description Signal input Gate control B Signal output GND Clock input Gate control A Power supply (5V) Auto-bias DC output 600 to 200k > 100k 40 to 500 Impedance > 10k at no clamp
Description of I/O Signals Input signals are low level clamped and output signals are inverted in relation to the input signals. Also, the clamp condition of input signals are controlled by VGB (Pin 2) conditions. 0V ........ Internal clamp condition 5V ........ Non internal clamp condition Center biased to approx. 2.1V by means of the IC internal resistance (approx. 10k). In this mode, the input signal is limited to APL 50% and the maximum input signal amplitude is 200mVp-p.
Input waveform
Output waveform
Clamp level
Electrical Characteristics (Ta = 25C, VDD = 5V, fCLK = 8.867238MHz, VCLK = 500mVp-p, sine wave) See "Electrical Characteristics Test Circuit" Item Supply current Low frequency gain Frequency response S/H pulse coupling S/N ratio Symbol IDD GL fg CP SN LIS Linearity LIL LIC Test condition -- SW condition 1 a 2 a a a 3 b b a a a b b b 4 a a b b b a a a 5 -- b b a c a a a -- 2.1 2.1 Bias condition V1 (V)
Min. Typ. Max. Unit Note
7 -2
12 0
17 2 0
mA dB dB
1 2 3 4 5
200kHz, a 500mVp-p, sine wave 200kHz 2MHz, b 150mVp-p, sine wave c No signal input No signal input 5-staircase wave (For luminance signals only)
-1.8 -1.8 -- 54 37 18 56 -- 56 40 20 60
--b --b b b b a a a
350 mVp-p -- 43 22 64 % dB
6
-2-
CXL5508M/P
Notes (1) This is the IC supply current value during clock and signal input. (2) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin. GL = 20 log OUT pin output voltage [mVp-p] [dB] 500 [mVp-p]
(3) Indicates the dissipation at 2MHz in relation to 200kHz. From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p, 2MHz sine wave is fed to same, cal culation is made according to the following formula. Input bias is tested at 2.1V. fg = 20 log OUT pin otuput voltage (2MHz) [mVp-p] [dB] OUT pin output voltage (200kHz) [mVp-p]
(4) The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. Input bias is tested at 2.1V.
Test value (mVp-p)
(5) Input no signal noise components are tested with the video noise meter at BPF 10kHz to 3MHz. This is calculated from the output gain (GL), at the input of 200kHz, 500mVp-p and according to the following formula. S/N = -20 * Iog Noise (mVrms) [dB] 0.5 * 10 GL/20
(6) Respective outputs are tested at the input of the 5-staircase waves seen in the figure below (Iuminance signals only) and calculated according to the formula below. (However, output signals become inverted with regards to input.)
Va 100 IRE Vc Vp Vs 40 IRE 500mV
LIS = Vs x 100 [%] Va LIL = Vp x 100 [%] Va
LIC = Vc x 100 [%] Va
-3-
CXL5508M/P
Clock
2fsc (8.867238MHz) sine wave
0.3 to 1.0Vp-p (0.5Vp-p typ.)
-4-
Electrical Characteristics Test Circuit
CLK 2fSC (8.867238MHz) 0.5Vp-p sine wave
3.3 1000p
1000p
200kHz 500mVp-p sine wave 1 8 AB 9V b IN VGB 2 3 4 OUT VSS 1 a SW2 b 1 SW3 a a 1M Note) b 1k b SW4 1000p 2.1k Note) SW5 c BPF x3 VDD CLK VGA a 7 6 5 0.1
a
200kHz 150mVp-p sine wave
b
Oscilloscope
Spectrum analyzer
-5-
V1 5V
SW1
2MHz 150mVp-p sine wave
c
Noise meter
d
5-staircase wave
[dB] BPF frequency response 0 -3
-50 10k 3M Frequency [Hz] 8.9M
CXL5508M/P
Application Circuit
2fSC 0.5Vp-p sine wave
5V 3.3 1000p
1 1000p 12 7 6 10 5 0.1 8
-6-
1 2 3 4 2.2k LPF PNP: 2SA1175 Delay time 140ns
Input
1 5V 2.2k
1M
Output 2.2k 2.2k
NPN: 2SC2785 Output
CXL5508M/P
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXL5508M/P
Example of Representative Characteristics
Supply current vs. Supply voltage
20 0.5
Low frequency gain vs. Supply voltage
10
Low frequency gain [dB]
5 Supply voltage [V] 5.25
15
0
Supply current [mA]
-0.5
5
-1
0 4.75
-1.5 4.75
5 Supply voltage [V]
5.25
Frequency response vs. Supply voltage
0.5 44
Linearity (LIS) vs. Supply voltage
Frequency response [dB]
0
Linearity (LIS) [%]
5 Supply voltage [V] 5.25
40
-0.5
36
-1
-1.5 4.75
32 4.75
5 Supply voltage [V]
5.25
Linearity (LIL) vs. Supply voltage
30 70
Linearity (LIC) vs. Supply voltage
66 25
Linearity (LIC) [%]
5 Supply voltage [V] 5.25
Linearity (LIL) [%]
62
20
58
15 54
10 4.75
50 4.75
-7-
5 Supply voltage [V]
5.25
CXL5508M/P
Supply current vs. Ambient temperature
20
Low frequency gain vs. Ambient temperature
0.5
10
Low frequency gain [dB]
0 10 20 30 40 50 Ambient temperature [C] 60 70
15
0
Supply current [mA]
-0.5
5
-1
0 -20 -10
-1.5 -20 -10
0
10 20 30 40 50 Ambient temperature [C]
60
70
Frequency response vs. Ambient temperature
0.5 44
Linearity (LIS) vs. Ambient temperature
Frequency response [dB]
0
Linearity (LIS) [%]
40
-0.5
36
-1
-1.5 -20 -10
0
10 20 30 40 50 Ambient temperature [C]
60
70
32 -20 -10
0
10 20 30 40 50 Ambient temperature [C]
60
70
Linearity (LIL) vs. Ambient temperature
30 70
Linearity (LIC) vs. Ambient temperature
66 25
Linearity (LIC) [%]
0 10 20 30 40 50 Ambient temperature [C] 60 70
Linearity (LIL) [%]
62
20
58
15 54
10 -20 -10
50 -20 -10
-8-
0 10 20 30 40 50 Ambient temperature [C]
60
70
CXL5508M/P
Package Outline CXL5508M
Unit: mm
8PIN SOP (PLASTIC)
+ 0.4 6.1 - 0.1 + 0.4 1.85 - 0.15
8
5 0.15 + 0.2 0.1 - 0.05
+ 0.3 5.3 - 0.1
7.9 0.4
1 0.45 0.1
4 + 0.1 0.2 - 0.05 1.27
6.9
0.24 M
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-8P-L01 SOP008-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.1g
CXL5508P
8PIN DIP (PLASTIC)
8
5
7.62
+ 0.3 6.4 - 0.1
+ 0.4 9.4 - 0.1
+ 0.1 0.05 0.25 -
0 to 15
EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.5g
1 2.54
4
0.5 0.1 1.2 0.15
3.0 MIN
0.5 MIN
+ 0.4 3.7 - 0.1
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-8P-01 DIP008-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
-9-
0.5 0.2

▲Up To Search▲

Price & Availability of CXL5508M

	To Download CXL5508M Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .